This invention relates to a data pulse receiver arrangement of a type suitable for the acquisition of data pulses which occur in a serial bit stream in a received information signal in which one level of the signal (say high) represents a binary value `1` and another level (say low) of the signal represents a binary value `0`, said arrangement including a data pulse clock generator in the form of a ringing circuit which comprises a tuned circuit arranged for oscillation at a predetermined clock pulse frequency and voltage-to-current convertor means responsive to voltage input pulses derived from received data pulses to produce current pulses for exciting the tuned circuit to maintain its oscillation.
A data pulse receiver arrangement of the above type has application in data transmission systems in which data transmission and reception is not synchronised, so that for data reception a data pulse clock has to be derived from the received data pulses. Such a data transmission system is, for example, the BBC/IBA Teletext television transmission system in which coded data pulses representing alpha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals representing normal picture information are present. United Kingdom patent specification No. 1,370,535 discloses this form of television transmission system, and the use of a data pulse receiver arrangement of the above type has already been proposed for generating a data pulse clock in a television receiver arrangement thereof.
However, in a received information signal, a succession of `1` data pulses and likewise a succession of `0` data pulses would cause the information signal to remain at one level, (e.g. high or low as the case may be) for the duration of such a succession of data pulses. This situation can give rise to difficulty in the reception and acquisition of the data pulses. Another situation that can give rise to difficulty is one in which the change in the level of the information signal is too frequent due to the reception of a relatively long series of alternate `1` and `0` data pulses. These difficulties arise from the use as the data pulse clock generator of a ringing circuit which oscillates at the desired clock frequency and which is excited to maintain its oscillation each time there is a change in the level of the information signal. Thus, if the change in level of the information signal is too frequent there is a possibility of over-exciting the ringing circuit so that the tuned circuit of the ringing circuit is distorted and its Q is reduced. On the other hand, if the change in level of the information signal is too infrequent there is then the possibility that oscillatory output of the ringing circuit is progressively damped.